Advanced digital design with the verilog hdl
Guardat en:
| Autor principal: | |
|---|---|
| Idioma: | anglès |
| Publicat: |
New Delhi
Prentice Hall of India
2005
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| Matèries: | |
| Etiquetes: |
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MARC
| LEADER | 00000am aa2200000a 44500 | ||
|---|---|---|---|
| 001 | OHA-20260330-1323 | ||
| 003 | OSt | ||
| 005 | 20260619090850.0 | ||
| 008 | 260619b |||||||| |||| 00| 0 eng d | ||
| 020 | |a 81-203-2756-X | ||
| 100 | |a Ciletti, Michael D | ||
| 245 | |a Advanced digital design with the verilog hdl | ||
| 260 | |a New Delhi |b Prentice Hall of India |c 2005 | ||
| 942 | |c BK | ||
| 952 | |0 0 |1 0 |4 0 |6 621_392000000000000_C572 |7 0 |9 81469 |a MSIT |b MSIT |c GEN |d 2026-03-30 |g 495.00 |l 0 |o 621.392 C572 |p 19997 |r 2026-03-30 21:22:13 |t 1 |v 495.00 |w 2026-03-30 |y BK | ||
| 952 | |0 0 |1 0 |4 0 |6 621_392000000000000_C572 |7 0 |9 81470 |a MSIT |b MSIT |c GEN |d 2026-03-30 |g 495.00 |l 7 |o 621.392 C572 |p 34001 |r 2026-04-18 15:58:37 |s 2026-04-18 |t 2 |v 495.00 |w 2026-03-30 |y BK | ||
| 952 | |0 0 |1 0 |4 0 |6 621_392000000000000_C572 |7 0 |9 81471 |a MSIT |b MSIT |c GEN |d 2026-03-30 |g 495.00 |l 0 |o 621.392 C572 |p 34002 |r 2026-03-30 21:22:13 |t 3 |v 495.00 |w 2026-03-30 |y BK | ||
| 952 | |0 0 |1 0 |4 0 |6 621_392000000000000_C572 |7 0 |9 81472 |a MSIT |b MSIT |c REF |d 2026-03-30 |g 495.00 |l 0 |o 621.392 C572 |p 34003 |r 2026-03-30 21:22:13 |t 4 |v 495.00 |w 2026-03-30 |y REF | ||
| 952 | |0 0 |1 0 |4 0 |6 621_392000000000000_C572 |7 0 |9 81473 |a MSIT |b MSIT |c GEN |d 2026-03-30 |g 495.00 |l 2 |o 621.392 C572 |p 34004 |r 2026-04-16 11:21:35 |s 2026-04-16 |t 5 |v 495.00 |w 2026-03-30 |y BK | ||
| 952 | |0 0 |1 0 |4 0 |6 621_392000000000000_C572 |7 0 |9 81474 |a MSIT |b MSIT |c GEN |d 2026-03-30 |g 495.00 |l 1 |o 621.392 C572 |p 34005 |r 2026-04-06 13:08:29 |s 2026-04-06 |t 6 |v 495.00 |w 2026-03-30 |y BK | ||
| 999 | |c 4548 |d 4548 | ||
| 650 | 0 | |a ECE : VHDL. | |